PR1168445 - Consulting and design services for the project Concept development of a Design-for-Test

CN-GEN-STDContract notice – general directive, standard regimepr1168445FVFraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V.
8 days left
Estimated value
Deadline8 days left27 Jul 2026, 09:00
Competition00 participants
Lots22 lots

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Key information

Identifier
pr1168445
Contract type
Deadline
27 Jul 2026, 09:00
CPV codes
73100000 - Research and experimental development services
Status
UNKN
Notice type
CN-GEN-STDContract notice – general directive, standard regime
Estimated value
Publication date
24 Jun 2026, 13:04

Overview

The two projects named above are cyber-security applications to fullfill requirements for the European Cyber-Security-Act. They will be developed in 22 nm FD-SOI silicon technology and beyond. To assure testability on block level up to system on chip top level, a strategy for DFT insertion and simulation must be developed and implemented. Therefore, one meeting per quarter shall be performed at the Fraunhofer Institute for Integrated Circuits in Erlangen-Tennenlohe. Furthermore, flexibility of working hours is required in order to be able to react promptly to urgent adjustments.

Erlangen, Germany

The following tasks are initially planned: • Setup of verification environment, server and simulation tool infrastructure • Familiarization with the design functionalities algorithms, structure and design hierarchy • Setup of test plans for hierarchical block level verification with UVM • Continuous development of testcases and execution of simulations, analysis and documentation of the verification results, support of bug fixing with the IIS design team • The progress and results of the described tasks will be the starting point for the definition of the following work III. Essential requirements • At least 10 years of experience in digital functional verification • At least 10 years of experience using standard functional verification and simulation tools from major providers like Synopsys, Cadence or Siemens-Mentor • At least 10 years of experience of setting up and use of verification environments and regression suites • Deep knowledge and experience in UVM verification methodology • Excellent analysis and documentation skills • Business fluent in German and English

Erlangen, Germany

#Besonders auch geeignet für:other-sme#

The following tasks are initially planned: • Setup of DFT environment for implementation and simulation with Cadence or Siemens EDA depending on the projects requirements o E.g. JTAG, MBIST, SCAN,… • Defining a DFT strategy for the individual projects • Familiarization with the project’s functionality, structure and design hierarchy • Continuous and iterative improvement of the test coverage • The progress and results of the described tasks will be the starting point for the definition of the following work III. Essential requirements • At least 10 years of experience in complex digital Design-for-Test • At least 10 years of experience in developing a proper Test strategy with Frontend Designers • In-depth knowledge about the different Test capabilities • Excellent analysis and documentation skills • Business fluent in English, German is a plus

Erlangen, Germany

#Besonders auch geeignet für:other-sme#

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Timeline

24 Jun 2026, 13:04

Issued at

Publication

25 Jun 2026, 00:00

Requested publication date

Publication

27 Jul 2026, 09:00

LOT-0002 Tender submission deadline period

Deadline

27 Jul 2026, 09:00

LOT-0001 Tender submission deadline period

Deadline

01 Oct 2026, 00:00

LOT-0002 - Procurement project planned period start

Milestone

01 Oct 2026, 00:00

LOT-0001 - Procurement project planned period start

Milestone

30 Sept 2028, 00:00

LOT-0001 - Procurement project planned period end

Deadline

30 Sept 2028, 00:00

LOT-0002 - Procurement project planned period end

Deadline

Version history

None recorded.

Contracting authorities1

Lots2

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